1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor wafer substrates. More particularly, the invention relates to the fabrication of silicon wafer substrates under conditions which control the concentration of internal gettering sites.
Single-crystal silicon, the starting material for most semiconductor fabrication processes, is most commonly prepared by the Czochralski method wherein a single seed crystal is dipped into molten silicon and slowly withdrawn. By rotating the crystal, a cylindrical ingot having a desired diameter is produced. The molten silicon is held in a quartz crucible.
Although characterized by very high purity, Czochralski method silicon crystals have a certain level of impurities. Most importantly, oxygen derived from the quartz crucible is present in concentrations from about 10 to 20 ppma. Such concentrations are above solid solubility at temperatures typical for integrated circuit manufacture processes. Being in supersaturated solution, the oxygen atoms will tend to precipitate. The precipitation of oxygen provides trapping sites for impurities detrimental for the performance of integrated circuits. This technique for removing impurities away from the vicinity of the active wafer surface by oxygen precipitation is referred to as "internal gettering."
Heretofore, the benefits associated with gettering caused by internal oxygen precipitation clusters have been somewhat serendipitous. Although the initial concentration of dissolved oxygen in the silicon ingots may be controlled, the concentration of gettering sites which are generated on subsequent thermal treatment of individual wafers depends on a number of factors and will vary widely. Thus, while the optimum concentration of gettering sites for a particular application may be known, the actual concentration present in a wafer undergoing processing has been very difficult to adjust to a specific concentration.
It would therefore be desirable to provide methods for controlling the concentration of gettering sites present in semiconductor substrates. More particularly, it would be desirable to provide methods capable of controlling the concentration of oxygen precipitation sites within silicon substrates prepared by the Czochralski method and other conventional silicon preparation methods.
2. Description of the Background Art
Hawkins and Lavine (1987) Materials Research Society Mtg., Nov. 30-Dec. 5, demonstrate a putative heterogeneous nucleation mechanism for oxygen in silicon by subjecting a wafer first to a rapid thermal anneal followed by annealing at 950.degree. C. for one hour and 1200.degree. C. for 13 hours. No optimization of internal gettering site concentration is disclosed. Alvi et al. (1987) Electrochemical Society Mtg., Oct. 18-23, describe the effect of rapid thermal annealing on the dissolution of metallic precipitates in silicon wafers. Hahn et al. (1986) Material Research Society Symp. Proc. 59:287-292, describe the formation of thermal donors by the annealing of silicon wafers at 450.degree. C., followed by rapid thermal annealing at 600.degree. C. to 1000.degree. C., followed further by two-step furnace annealing at 700.degree. C. and 950.degree. C. The paper does not consider the desirability of re-establishing a desired concentration of oxygen precipitates. Chang-Outu and Tobin (1986) J. Electrochem. Soc. 133:2147-2152, suggests that the precipitation of oxygen in wafer fabrication processes depends strongly on the initial concentration of dissolved oxygen in the silicon. An initial oxygen concentration in the range from about 14 to 16 ppma is taught to be optimum for subsequent gettering of impurities. Jastrzebski et al. (1984) J. Electrochem. Soc. 131:2944-2953 suggest a correlation between the amount of precipitated oxygen and the particular conditions of silicon wafer fabrication. Inoue et al. (1981) in "Semiconductor Silicon 1981", ed. Huff et al., Proc. Vol. 81-5, The Electrochemical Society, pp 282-293, teaches that the concentration of oxygen precipitates in a silicon wafer can be increased by low temperature annealing. Finally, U.S. Pat. No. 4,608,095, relates to external gettering by providing a layer of polysilicon on the rear surface of the wafer.